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1 ltc1553l 5-bit programmable synchronous switching regulator controller for pentium ? ii processor features descriptio n u n 5-bit digitally programmable 1.8v to 3.5v fixed output voltage n provides all features required by the intel pentium ? ii processor vrm 8.2 dc/dc converter specification n flags for power good, over-temperature and overvoltage fault n 19a output current capability from a 5v supply n dual n-channel mosfet synchronous driver n initial output accuracy: 1.5% n excellent output accuracy: 2% typ over line, load and temperature variations n high efficiency: over 95% possible n adjustable current limit without external sense resistors n fast transient response n available in 2o-lead ssop and sw packages the ltc ? 1553l is a high power, high efficiency switching regulator controller optimized for a 5v input to 1.8v-3.5v output applications. it features a digitally programmable output voltage, a precision internal reference and an internal feedback system that provides output accuracy of 1.5% at room temperature and typically 2% over-temperature, load current and line voltage shifts. the ltc1553l uses a syn- chronous switching architecture with two external n-channel output devices, providing high efficiency and eliminating the need for a high power, high cost p-channel device. addition- ally, it senses the output current across the on-resistance of the upper n-channel fet, providing an adjustable current limit without an external low value sense resistor. the ltc1553l free-runs at 300khz and can be synchronized to a faster external clock if desired. it includes all the inputs and outputs required to implement a power supply conform- ing to the intel pentium ? ii processor vrm 8.2 dc/dc converter specification . applicatio n s u n power supply for pentium ii, sparc, alpha and pa-risc microprocessors n high power 5v to 1.8v-3.5v regulators typical applicatio n u figure 1. 5v to 1.8v-3.5v supply application , ltc and lt are registered trademarks of linear technology corporation. pentium is a registered trademark of intel corporation. pwrgd fault ot vid0 to vid4 outen comp ss sgnd gnd sense 10 m f q1* 20 w q2* 0.1 m f v cc i max pv cc pv cc 12v v in 5v l o ? 2 m h 18a ltc1553l g1 i fb g2 + 0.1 m f 1553l f01 c c 0.01 m f r c 8.2k 5.6k 2.7k 5.6k 5.6k c ss 0.1 m f 0.1 m f 10 m f c in ** 1200 m f 4 v out 1.8v to 3.5v 14a c out ?? 330 m f 7 + + c1 150pf + 5 pentium ii system * siliconix sud50n03-10 ** sanyo 10mv1200gx ? coiltronics ctx02-13198 or panasonic 12ts-2r5sp ?? avx tpse337m006r0100
2 ltc1553l absolute m axi m u m ratings w ww u order part number (note 1) supply voltage v cc ........................................................................ 7v pv cc ................................................................... 14v input voltage i fb (note 2) ............................................ pv cc + 0.3v i max ........................................................ C 0.3v to 9v all other inputs ......................... C 0.3v to v cc + 0.3v digital output voltage ................................. C 0.3v to 9v i fb input current (notes 2, 3) .......................... C 100ma operating temperature range ..................... 0 c to 70 c storage temperature range ................. C 65 c to 150 c lead temperature (soldering, 10 sec.)................. 300 c package/order i n for m atio n w u u v cc = 5v, pv cc = 12v, t a = 25 c, unless otherwise noted. (note 3) electrical characteristics consult factory for industrial and military grade parts. ltc1553lcg ltc1553lcsw symbol parameter conditions min typ max units v cc supply voltage l 4.5 6 v pv cc supply voltage for g1, g2 l 13.2 v v fb internal feedback voltage (note 4) 1.260 v v out 1.8v initial output voltage with respect to rated output voltage (figure 2) C 27 (C 1.5%) 27 (+ 1.5%) mv 2.8v initial output voltage C 42 (C 1.5%) 42 (+ 1.5%) mv 3.5v initial output voltage C 52 (C 1.5%) 52 (+ 1.5%) mv 1.8v initial output voltage l C 36 (C 2%) 36 (+ 2%) mv 2.8v initial output voltage l C 56 (C 2%) 56 (+ 2%) mv 3.5v initial output voltage l C 70 (C 2%) 70 (+ 2%) mv d v out output load regulation i out = 0 to 14a (note 4) (figure 2) C 5 mv output line regulation v in = 4.75v to 5.25v, i out = 0 (note 4)(figure 2) 1mv v pwrgd positive power good trip point % above output voltage (figure 2) l 57 % negative power good trip point % below output voltage (figure 2) l C7 C5 % v fault fault trip point % above output voltage (figure 2) l 12 15 20 % i cc operating supply current outen = v cc = 5v (note 5)(figure 3) l 800 1200 m a shutdown supply current outen = 0, vid0 to vid4 floating (figure 3) l 130 250 m a i pvcc supply current pv cc = 12v, outen = v cc (note 6) (figure 3) 15 ma pv cc = 12v, outen = 0, vid0 to vid4 floating 1 m a f osc internal oscillator frequency (figure 4) l 250 300 350 khz v sawl v comp at minimum duty cycle (note 4) 1.8 v v sawh v comp at maximum duty cycle (note 4) 2.8 v g err error amplifier open-loop dc gain (note 7) l 40 53 db g merr error amplifier transconductance (note 7) l 0.9 1.6 2.3 millimho bw err error amplifier C3db bandwidth comp = open (note 4) 400 khz 1 2 3 4 5 6 7 8 9 10 top view g package 20-lead plastic ssop sw package 20-lead plastic so 20 19 18 17 16 15 14 13 12 11 g2 pv cc gnd sgnd v cc sense i max i fb ss comp g1 outen vid0 vid1 vid2 vid3 vid4 pwrgd fault ot t jmax = 125 c, q ja = 100 c/ w (g) t jmax = 125 c, q ja = 100 c/ w (sw)
3 ltc1553l symbol parameter conditions min typ max units i imax i max sink current v imax = v cc l 150 180 220 m a i ss soft start source current v ss = 0v, v imax = 0v, v ifb = v cc l C15 C11 C8 m a i ssil maximum soft start sink current v sense = v out , v imax = v cc , v ifb = 0v l 30 60 150 m a under current limit (notes 8, 9), v ss = v cc i sshil soft start sink current under hard v sense = 0v, v imax = v cc , v ifb = 0v l 20 45 ma current limit t sshil hard current limit hold time v sense = 0v, v imax = 4v, v ifb from 5v (note 4) 500 m s t pwrgd power good response time - v sense - from 0v to rated v out l 0.5 1 2 ms t pwrbad power good response time v sense from rated v out to 0v l 200 500 1000 m s t fault fault response time v sense - from rated v out to v cc l 200 500 1000 m s t ot ot response time outen , vid0 to vid4 = 0 (note 10) (figure 3) l 15 40 60 m s v ot over-temperature trip point outen , vid0 to vid4 = 0 (note 10) (figure 3) l 1.9 2 2.12 v v otdd over-temperature driver disable outen , vid0 to vid4 = 0 (note 10) (figure 3) l 1.6 1.7 1.8 v v shdn shutdown outen , vid0 to vid4 = 0 (note 10) (figure 3) l 0.8 v t r , t f driver rise and fall time (figure 4) l 90 150 ns t nol driver nonoverlap time (figure 4) l 30 100 ns dc max maximum g1 duty cycle (figure 4) l 77 85 90 % v ih vid0 to vid4 input high voltage l 2v v il vid0 to vid4 input low voltage l 0.8 v r in vid0 to vid4 internal pull-up l 10 20 k w resistance i sink digital output sink current l 10 ma electrical characteristics v cc = 5v, pv cc = 12v, t a = 25 c, unless otherwise noted. (note 3) the l denotes specifications which apply over the full operating temperature range. note 1: absolute maximum ratings are those values beyond which the life of a device may be impaired. note 2: when i fb is taken below gnd, it will be clamped by an internal diode. this pin can handle input currents greater than 100ma below gnd without latchup. in the positive direction, it is not clamped to v cc or pv cc . note 3: all currents into device pins are positive; all currents out of the device pins are negative. all voltages are referenced to ground unless otherwise specified. note 4: this parameter is guaranteed by correlation and is not tested directly. note 5: the ltc1553l goes into the shutdown mode if vid0 to vid4 are floating. due to the internal pull-up resistors, there will be an additional 0.25ma/pin if any of the vid0 to vid4 pins are pulled low. note 6 : supply current in normal operation is dominated by the current needed to charge and discharge the external fet gates. this will vary with the ltc1553l operating frequency, supply voltage and the external fets used. note 7: the open-loop dc gain and transconductance from the sense pin to comp pin will be (g err )(1.260/3.3) and (g merr )(1.260/3.3) respectively. note 8: the current limiting amplifier can sink but cannot source current. under normal (not current limited) operation, the output current will be zero. note 9: under typical soft current limit, the net soft start discharge current will be 60 m a (i ssil ) + [C 11 m a(i ss )] @ 50 m a. the soft start sink-to-source current ratio is designed to be 5.5:1. note 10: when vid0 to vid4 are all high, the ltc1553l will be forced to shut down internally. the outen trip voltages are guaranteed by design for all other input codes.
4 ltc1553l typical perfor m a n ce characteristics uw typical 2.8v v out distribution load regulation over-temperature trip point vs temperature efficiency vs load current line regulation output temperature drift error amplifier open-loop dc gain vs temperature over-temperature driver disable vs temperature error amplifier transconductance vs temperature output voltage (v) 2.775 0 number of units 20 60 80 100 140 1553l g01 40 120 2.795 2.825 2.785 2.805 2.815 total sample size = 1500 25 c 100 c load current (a) 0 efficiency (%) 60 80 100 4 1533l g02 40 20 50 70 90 a 30 10 0 0.3 2 6 8 10 12 14 b refer to typical application circuit figure 1 v in = 5v, pv cc = 12v, v out = 2.8v, c out = 330 m f 7, l o = 2 m h a: q1 = 1 sud50n03-10 q2 = 1 sud50n03-10 b: q1 = 2 sud50n03-10 q2 = 1 sud50n03-10 no fan q1 is mounted on 1in 2 copper area output current (a) 0 output voltage (v) 2.825 4 1533l g03 2.820 2.815 2.810 2.805 2.800 2.795 2.790 2.785 2.780 2.775 1 2 3 5 67891011121314 refer to typical application circuit figure 1 v in = 5v, pv cc = 12v, t a = 25 c input voltage (v) 4.75 output voltage (v) 2.825 2.820 2.815 2.810 2.805 2.800 2.795 2.790 2.785 2.780 2.775 5.15 1553l g04 4.85 4.95 5.05 5.25 refer to typical application circuit figure 1 output = no load t a = 25 c temperature ( c) ?0 output voltage (v) 2.860 2.850 2.840 2.830 2.820 2.810 2.800 2.790 2.780 2.770 2.750 2.660 2.740 0 50 75 1553l g05 ?5 25 100 125 temperature ( c) ?0 over-temperature trip point (v) 1.96 2.08 2.10 2.12 0 50 75 1553l g06 1.92 2.04 2.00 1.94 2.06 1.90 2.02 1.98 ?5 25 100 125 temperature ( c) ?0 1.60 over-temperature driver disable (v) 1.62 1.66 1.68 1.70 1.80 1.74 0 50 75 1553l g07 1.64 1.76 1.78 1.72 ?5 25 100 125 temperature ( c) ?0 1.7 1.9 2.3 25 75 1553l g08 1.5 1.3 ?5 0 50 100 125 1.1 0.9 2.1 error amplifier transconductance (millimho) temperature ( c) ?0 40 error amplifier open-loop dc gain (db) 45 50 55 60 ?5 0 25 50 1553l g09 75 100 125
5 ltc1553l typical perfor m a n ce characteristics uw soft start source current vs temperature oscillator frequency vs temperature i max sink current vs temperature v cc shutdown supply current vs temperature v cc operating supply current vs temperature output over current protection 50mv/div 5a/div 100 m s/div 1553l g18 transient response temperature ( c) ?0 250 oscillator frequency (khz) 260 280 290 300 350 320 0 50 75 1553l g10 270 330 340 310 ?5 25 100 125 temperature ( c) ?0 150 i max sink current ( m a) 160 170 180 220 200 ?5 25 50 125 1553l g11 210 190 0 75 100 temperature ( c) ?0 soft start source current ( m a) ? ? 25 75 1553l g12 ?0 ?1 ?5 0 50 100 125 ?2 ?3 ?4 ?5 temperature ( c) ?0 maximum g1 duty cycle (%) 25 75 1553l g13 ?5 0 50 100 125 88 90 92 86 84 82 80 78 oscillator frequency = 300khz g1, g2 capacitance = 1100pf 5500pf 7700pf 2200pf 3300pf maximum g1 duty cycle vs temperature temperature ( c) ?0 0.9 1.0 1.2 25 75 1553l g14 0.8 0.7 ?5 0 50 100 125 0.6 0.5 1.1 v cc operating supply current (ma) v cc = 5v f osc = 300khz temperature ( c) ?0 v cc shutdown supply current (ma) 225 25 1553l g15 150 100 ?5 0 50 75 50 250 200 175 125 75 100 125 pv cc supply current vs gate capacitance gate capacitance (pf) 0 pv cc supply current (ma) 40 50 60 6000 1553l g16 30 20 2000 4000 8000 10 0 70 pv cc = 12v t a = 25 c output current (a) 0 0 output voltage (v) 0.5 1.5 2.0 2.5 4 8 10 18 1553l g17 1.0 26 12 14 16 3.0 q1 case = 90 c, v out = 2.8v q1 = 2 mtd20n03hdl q2 = 1 mtd20n03hdl r imax = 2.7k, r ifb = 20 w , ss cap = 0.01 m f short-circuit current
6 ltc1553l g2 (pin 1): gate drive for the lower n-channel mosfet, q2. this output will swing from pv cc to gnd. it will always be low when g1 is high or when the output is disabled. to prevent undershoot during a soft start cycle, g2 is held low until g1 first goes high. pv cc (pin 2): power supply for g1 and g2. pv cc must be connected to a potential of at least v in + v gs(on)q1 . if v in = 5v, pv cc can be generated using a simple charge pump connected to the switching node between q1 and q2 (see figure 7), or it can be connected to an auxiliary 12v supply if one exists. gnd (pin 3): power ground. gnd should be connected to a low impedance ground plane in close proximity to the source of q2. sgnd (pin 4): signal ground. sgnd is connected to the low power internal circuitry and should be connected to the negative terminal of the output capacitor where it returns to the ground plane. gnd and sgnd should be shorted right at the ltc1553l. v cc (pin 5): power supply. power for the internal low power circuity. v cc should be wired separately from the drain of q1 if they share the same supply. a 10 m f bypass capacitor is recommended from this pin to sgnd. sense (pin 6): output voltage pin. connect to the positive terminal of the output capacitor. there is an internal 120k resistor connected from this pin to sgnd. sense is a very sensitive pin; for optimum performance, connect an exter- nal 0.1 m f capacitor from this pin to sgnd. by connecting a small external resistor between the output capacitor and the sense pin, the initial output voltage can be raised slightly. since the internal divider has a nominal imped- ance of 120k w , a 1200 w series resistor will raise the nominal output voltage by 1%. if an external resistor is used, the value of the 0.1 m f capacitor on the sense pin must be greatly reduced or loop phase margin will suffer. set a time constant for the rc combination of approxi- mately 0.1 m s. so, for example, with a 1200 w resistor, set c = 83pf. use a standard 100pf capacitor. pi n fu n ctio n s uuu i max (pin 7): current limit threshold. current limit is set by the voltage drop across an external resistor connected between the drain of q1 and i max . there is a 180 m a internal pull-down at i max . i fb (pin 8): current limit sense pin. connect to the switching node between the source of q1 and the drain of q2. if i fb drops below i max when g1 is on, the ltc1553l will go into current limit. the current limit circuit can be disabled by floating i max and shorting i fb to v cc through an external 10k resistor. ss (pin 9): soft start. connect to an external capacitor to implement a soft start function. during moderate overload conditions, the soft start capacitor will be discharged slowly in order to reduce the duty cycle. in hard current limit, the soft start capacitor will be forced low immedi- ately and the ltc1553l will rerun a complete soft start cycle. c ss must be selected such that during power-up the current through q1 will not exceed the current limit value. comp (pin 10): external compensation. the comp pin is connected directly to the output of the error amplifier and the input of the pwm comparator. an rc + c network is used at this node to compensate the feedback loop to provide optimum transient response. ot (pin 11): over-temperature fault. ot is an open-drain output and will be pulled low if outen is less than 2v. if outen = 0, ot pulls low. fault (pin 12): overvoltage fault. fault is an open- drain output. if v out reaches 15% above the nominal output voltage, fault will go low and g1 and g2 will be disabled. once triggered, the ltc1553l will remain in this state until the power supply is recycled or the outen pin is toggled. if outen = 0, fault floats or is pulled high by an external resistor. pwrgd (pin 13): power good. this is an open-drain signal to indicate validity of output voltage. a high indi- cates that the output has settled to within 5% of the rated output for more than 1ms. pwrgd will go low if the output is out of regulation for more than 500 m s. if outen = 0, pwrgd pulls low.
7 ltc1553l pi n fu n ctio n s uuu vid0, vid1, vid2, vid3, vid4 (pins 18, 17, 16, 15, 14): digital voltage select. ttl inputs used to set the regulated output voltage required by the processor (table 3). there is an internal 20k w pull-up at each pin. when all five vid n pins are high or floating, the chip will shut down. outen (pin 19): output enable. ttl input which enables the output voltage. the external mosfet temperature can be monitored with an external thermistor as shown in figure 11. when the outen input voltage drops below 2v, ot trips. as outen drops below 1.7v, the drivers are internally disabled to prevent the mosfets from heating further. if outen is less than 1.2v for longer than 30 m s, the ltc1553l will enter shutdown mode. the internal oscillator can be synchronized to a faster external clock by applying the external clocking signal to the outen pin. g1 (pin 20): gate drive for the upper n-channel mosfet, q1. this output will swing from pv cc to gnd. it will always be low when g2 is high or the output is disabled. block diagra m w vid0 vid1 vid2 vid3 vid4 18 17 16 15 14 outen 19 comp ss pv cc g1 g2 1553 bd sense + fc + + pwm system power down r s disdr v ref i ss q ss 115% v ref v ref 0.5v ref / 0.7v ref hcl mono mhcl v ref ?5% v ref + 5% delay dac fb logic max + min + err + i max i max i fb pwrgd cc + lvc fault ot bg 10 9 12 11 13 2 20 1 6 8 7
8 ltc1553l test circuits figure 4 figure 3 figure 2 outen pwrgd fault ot vid0 to vid4 comp ss sgnd gnd sense q1* nc q2* v cc i fb pv cc 12v v cc 5v pv cc v in 5v l o ? 2 m h 15a ltc1553l g1 i max g2 0.1 m f 1553l f02 c c 0.01 m f r c 8.2k 3k 100pf 0.1 m f 0.1 m f 0.1 m f 10 m f 10 m f v out + c1 150pf 10k 3k 3k + + vid0 to vid4 100pf 100pf + c in ** 1200 m f 4 * siliconix sud50n03-10 ** sanyo 10mv1200gx ? coiltronics ctx02-13198 or panasonic 12ts-2r5sp ?? avx tpse337m006r0100 c out ?? 330 m f 7 outen pwrgd fault ot comp ss sgnd gnd sense 10 m f nc nc nc nc nc nc nc nc 0.1 m f v cc v cc v cc vid0 vid1 vid2 vid3 vid4 vid0 vid1 vid2 vid3 vid4 i fb pv cc ltc1553l pv cc g1 i max g2 1553l f03 0.1 m f 10 m f + + 10k v cc 5v pv cc 12v 0.1 m f 10 m f g2 rise/fall g1 rise/fall 5000pf 5000pf sgnd gnd sense 10 m f g2 g1 0.1 m f v cc i fb ltc1553l pv cc 1553l f04 90% t r t f t nol t nol 50% 10% 50% 50% 90% 50% 10% + + 10k
9 ltc1553l fu ctio tables u u table 1. ot logic outen (v) ot* < 2 0 > 2 1 table 2. pwrgd and fault logic input output* outen v sense ** ot fault pwrgd 0 x 010 1 < 95% 1 1 0 1 > 95% 1 1 1 < 105% 1 >105% 1 1 0 1 > 115% 1 0 0 table 3. rated output voltage input pin rated output v id4 v id3 v id2 v id1 v id0 voltage (v) 01111 disabled ? (1.30) 01110 disabled ? (1.35) 01101 disabled ? (1.40) 01100 disabled ? (1.45) 01011 disabled ? (1.50) 01010 disabled ? (1.55) 01001 disabled ? (1.60) 01000 disabled ? (1.65) 00111 disabled ? (1.70) 00110 disabled ? (1.75) 00101 1.80 00100 1.85 00011 1.90 00010 1.95 00001 2.00 00000 2.05 11111 shdn 11110 2.1 11101 2.2 11100 2.3 11011 2.4 11010 2.5 11001 2.6 11000 2.7 10111 2.8 10110 2.9 10101 3.0 10100 3.1 10011 3.2 10010 3.3 10001 3.4 10000 3.5 * with external pull-up resistor ** with respect to the output voltage selected in table 3 as required by intel specification vrm 8.2 ? these code selections are disabled in ltc1553l x dont care table 3. rated output voltage (cont) input pin rated output v id4 v id3 v id2 v id1 v id0 voltage (v)
10 ltc1553l applicatio n s i n for m atio n wu u u overview the ltc1553l is a voltage feedback, synchronous switch- ing regulator controller (see block diagram) designed for use in high power, low voltage step-down (buck) convert- ers. it is designed to satisfy the requirements of the intel pentium ii power supply specification. it includes an on-chip dac to control the output voltage, a pwm genera- tor, a precision reference trimmed to 1%, two high power mosfet gate drivers and all the necessary feedback and control circuitry to form a complete switching regulator circuit. the ltc1553l includes a current limit sensing circuit that uses the upper external power mosfet as a current sensing element, eliminating the need for an external sense resistor. once the current comparator, cc, detects an overcurrent condition, the duty cycle is reduced by discharging the soft start capacitor through a voltage- controlled current source. under severe overloads or output short circuit conditions, the chip will be repeatedly forced into soft start until the short is removed, preventing the external components from being damaged. under output overvoltage conditions, the mosfet drivers will be disabled permanently until the chip power supply is recycled or the outen pin is toggled. outen can optionally be connected to an external nega- tive temperature coefficient (ntc) thermistor placed near the external mosfets or the microprocessor. three thresh- old levels are provided internally. when outen drops to 2v, ot will trip, issuing a warning to the external cpu. if the temperature continues to rise and the outen input drops to 1.7v, the g1 and g2 pins will be forced low. if outen is pulled below 1.2v, the ltc1553l will go into shutdown mode, cutting the supply current to a minimum. if thermal shutdown is not required, outen can be con- nected to a conventional ttl enable signal. the free- running 300khz pwm frequency can be synchronized to a faster external clock connected to outen. adjusting the oscillator frequency can add flexibility in the external component selection. see the clock synchronization section. output regulation can be monitored with the pwrgd pin which in turn monitors the internal min and max com- parators. if the output is 5% beyond the selected value for more than 500 m s, the pwrgd output will be pulled low. once the output has settled within 5% of the selected value for more than 1ms, pwrgd will return high. theory of operation primary feedback loop the regulator output voltage at the sense pin is divided down internally by a resistor divider with a total resistance of approximately 120k w . this divided down voltage is subtracted from a reference voltage supplied by the dac output. the resulting error voltage is amplified by the error amplifier and the output is compared to the oscillator ramp waveform by the pwm comparator. this pwm signal controls the external mosfets through g1 and g2. the resulting chopped waveform is filtered by l o and c out closing the loop. loop frequency compensation is achieved with an external rc + c network at the comp pin, which is connected to the output node of the transconductance amplifier. min, max feedback loops two additional comparators in the feedback loop provide high speed fault correction in situations where the err amplifier may not respond quickly enough. min compares the feedback signal fb to a voltage 60mv (5%) below the internal reference. if fb is lower than the threshold of this comparator, the min comparator overrides the err amplifier and forces the loop to full duty cycle which is set by the internal oscillator typically to 85%. similarly, the max comparator forces the output to 0% duty cycle if fb is more than 5% above the internal reference. to prevent these two comparators from triggering due to noise, the min and max comparators response times are deliber- ately controlled so that they take two to three microsec- onds to respond. these two comparators help prevent extreme output perturbations with fast output transients, while allowing the main feedback loop to be optimally compensated for stability.
11 ltc1553l applicatio n s i n for m atio n wu u u soft start and current limit the ltc1553l includes a soft start circuit which is used for initial start-up and during current limit operation. the ss pin requires an external capacitor to gnd with the value determined by the required soft start time. an internal 11 m a current source is included to charge the external ss capacitor. during start-up, the comp pin is clamped to a diode drop above the voltage at the ss pin. this prevents the error amplifier, err, from forcing the loop to maxi- mum duty cycle. the ltc1553l will begin to operate at low duty cycle as the ss pin rises above about 1.2v (v comp ? 1.8v). as ss continues to rise, q ss turns off and the error amplifier begins to regulate the output. the min compara- tor is disabled when soft start is active to prevent it from overriding the soft start function. the ltc1553l includes yet another feedback loop to control operation in current limit. just before every falling edge of g1, the current comparator, cc, samples and holds the voltage drop measured across the external mosfet, q1, at the i fb pin. cc compares the voltage at i fb to the voltage at the i max pin. as the peak current rises, the measured voltage across q1 increases due to the drop across the r ds(on) of q1. when the voltage at i fb drops below i max , indicating that q1s drain current has ex- ceeded the maximum level, cc starts to pull current out of the external soft start capacitor, cutting the duty cycle and controlling the output current level. the cc comparator pulls current out of the ss pin in proportion to the voltage difference between i fb and i max . under minor overload conditions, the ss pin will fall gradually, creating a time delay before current limit takes effect. very short, mild overloads may not affect the output voltage at all. more significant overload conditions will allow the ss pin to reach a steady state, and the output will remain at a reduced voltage until the overload is removed. serious overloads will generate a large overdrive at cc, allowing it to pull ss down quickly and preventing damage to the output components. by using the r ds(on) of q1 to measure the output current, the current limiting circuit eliminates an expensive dis- crete sense resistor that would otherwise be required. this helps minimize the number of components in the high current path. due to switching noise and variation of r ds(on) , the actual current limit trip point is not highly accurate. the current limiting circuitry is primarily meant to prevent damage to the power supply circuitry during fault conditions. the exact current level where the limiting circuit begins to take effect will vary from unit to unit as the r ds(on) of q1 varies. for a given current limit level, the external resistor from i max to v in can be determined by: r ir i imax lmax ds on q imax = ()( ) ()1 where, ii i lmax load ripple =+ 2 i load = maximum load current i ripple = inductor ripple current = - ()() ()()() vv v flv in out out osc o in f osc = ltc1553l oscillator frequency = 300khz l o = inductor value r ds(on)q1 = hot on-resistance of q1 at i lmax i imax = internal 180 m a sink current at i max figure 5. current limit setting q1 180 m a g1 q2 c in l o v out 1553l f05 c out r imax v in + cc g2 20 w ltc1553l i max i fb 8 7 + +
12 ltc1553l table 4. recommended minimum r imax resistor (k w ) vs maximum operating load current and external mosfet q1 maximum operating sud50n03-10 mtd20n03hdl load current (a) sud50n03-10 (two in parallel) mtd20n03hdl (two in parallel) 12 2.4 1.2 4.3 2.2 14 2.7 1.3 5.1 2.7 16 3.0 1.5 6.2 3.0 18 3.6 1.8 6.8 3.3 20 3.9 2.0 7.5 3.6 applicatio n s i n for m atio n wu u u outen and thermistor input the ltc1553l includes a low power shutdown mode, controlled by the logic at the outen pin. a high at outen allows the part to operate normally. a low level at outen stops all internal switching, pulls comp and ss to ground internally and turns q1 and q2 off. ot and pwrgd are pulled low, and fault is left floating. in shutdown, the ltc1553l quiescent current will drop to about 130 m a. the remaining current is used to keep the thermistor sensing circuit at outen alive. note that the leakage current of the external mosfets may add to the total shutdown current consumed by the circuit, especially at elevated temperature. outen is designed with multiple thresholds to allow it to also be utilized for over-temperature protection. the power mosfet operating temperature can be monitored with an external negative temperature coefficient (ntc) thermistor mounted next to the external mosfet which is expected to run the hottest CC often the high-side device, q1. elec- trically, the thermistor should form a voltage divider with another resistor, r1, connected to v cc . their midpoint should be connected to outen (see figure 6). as the temperature increases, the outen pin voltage is reduced. under normal operating conditions, the outen pin should stay above 2v. all circuits will function normally, and the ot pin will remain in a high state. if the temperature gets abnormally high, the outen pin voltage will eventually drop below 2v. ot will switch to a logic low, providing an over-temperature warning to the system. as outen drops below 1.7v, the ltc1553l disables both fet drivers. if outen is less than 1.2v, the ltc1553l will enter shut- down mode. to activate any of these three modes, the outen voltage must drop below the respective threshold for longer than 30 m s. clock synchronization the internal oscillator can be synchronized to an external clock by applying the external clocking signal to the outen pin. the synchronizing range extends from the initial operating frequency up to 500khz. if the external frequency is much higher than the natural free-running frequency, the peak-to-peak sawtooth amplitude within the ltc1553l will decrease. since the loop gain is in- versely proportional to the amplitude of the sawtooth, the compensation network may need to be adjusted slightly. note that the temperature sensing circuitry does not operate when external synchronization is used. mosfet gate drive power for the internal mosfet drivers is supplied by pv cc . this supply must be above the input supply voltage by at least one power mosfet v gs(on) for efficient opera tion. this higher voltage can be supplied with a separate supply, or it can be generated using a simple charge pump as shown in figure 7. the 85% typical maximum duty cycle ensures sufficient off-time to refresh the charge pump during each cycle. q1 q2 l o v out 1553l f06 c out 5.6k v in v cc v cc r1 r2 ntc thermistor mount in close thermal proximity to q1 ltc1553l pentium ii system g1 g2 ot outen + figure 6. outen pin as a thermistor input
13 ltc1553l applicatio n s i n for m atio n wu u u r p dc q i vp vi r p dc q i vp vv i ds on q max q max in max q out max ds on q max q max in max q in out max () () () () () () = () [] () = () ? ? ()() = () [] () = () ? ? - ()() 1 1 2 1 2 2 2 2 2 2 1 2 p max should be calculated based primarily on required efficiency or allowable thermal dissipation. a typical high efficiency circuit designed for pentium ii with a 5v input and a 2.8v, 11.2a output might allow no more than 4% efficiency loss at full load for each mosfet. assuming roughly 90% efficiency at this current level, this gives a p max value of: [(2.8)(11.2a/0.9)(0.04)] = 1.39w per fet and a required r ds(on) of: r vw va r vw vv a ds on q ds on q () () = ()( ) ()( ) = = ()( ) - ()() = 1 2 2 2 5139 2 8 11 2 0 019 5139 528112 0 025 . .. . . .. . w w note also that while the required r ds(on) values suggest large mosfets, the dissipation numbers are only 1.39w per device or lessCClarge to-220 packages and heat sinks are not necessarily required in high efficiency applica- tions. siliconix si4410dy or international rectifier irf7413 (both in so-8) or siliconix sud50n03 or motorola mtd20n03hdl (both in d pak) are small footprint sur- face mount devices with r ds(on) values below 0.03 w at 5v of gate drive that work well in ltc1553l circuits. with higher output voltages, the r ds(on) of q1 may need to be significantly lower than that for q2. these conditions can often be met by paralleling two mosfets for q1 and using a single device for q2. note that using a higher p max value in the r ds(on) calculations will generally decrease mosfet cost and circuit efficiency while increasing mosfet heat sink requirements. q1 g1 q2 0.1 m f l o v out 1553l f07 c out c in v in pv cc 1n5243b 13v 1n5817 optional for v in > 5v g2 ltc1553l 20 1 2 + + figure 7. doubling charge pump if the outen pin is low, g1 and g2 are both held low to prevent output voltage undershoot. as v cc and pv cc power up from a 0v condition, an internal undervoltage lockup circuit prevents g1 and g2 from going high until v cc reaches about 3.5v. if v cc powers up while pv cc is at ground potential, the ss is forced to ground potential internally. ss clamps the comp pin low and prevents the drivers from turning on. on power-up or recovery from thermal shutdown, the drivers are designed such that g2 is held low until g1 first goes high. power mosfets two n-channel power mosfets are required for most ltc1553l circuits. logic level mosfets should be used and they should be selected based on on-resistance con- siderations. r ds(on) should be chosen based on input and output voltage, allowable power dissipation and maxi- mum required output current. in a typical ltc1553l buck converter circuit the average inductor current is equal to the output load current. this current is always flowing through either q1 or q2 with the power dissipation split up according to the duty cycle: dc q v v dc q v v vv v out in out in in out in 1 21 () = () =- = - () the r ds(on) required for a given conduction loss can now be calculated by rearranging the relation p = i 2 r.
14 ltc1553l applicatio n s i n for m atio n wu u u note: please refer to the manufacturers data sheet for testing conditions and detail information. inductor selection the inductor is often the largest component in the ltc1553l design and should be chosen carefully. inductor value and type should be chosen based on output slew rate require- ments, output ripple requirements and expected peak current. inductor value is primarily controlled by the required current slew rate. the maximum rate of rise of current in the inductor is set by its value, the input-to- output voltage differential and the maximum duty cycle of the ltc1553l. in a typical 5v input, 2.8v output applica- tion, the maximum current slew rate will be: dc vv ll a s max in out - () = 183 . m where l is the inductor value in m h. with proper frequency compensation, the combination of the inductor and output capacitor will determine the transient recovery time. in general, a smaller value inductor will improve transient response at the expense of increased output ripple voltage and inductor core saturation rating. a 2 m h inductor would have a 0.9a/ m s rise time in this application, resulting in a 5.5 m s delay in responding to a 5a load current step. during this 5.5 m s, the difference between the inductor current and the output current must be made up by the output capaci- tor, causing a temporary voltage droop at the output. to minimize this effect, the inductor value should usually be in the 1 m h to 5 m h range for most typical 5v input ltc1553l circuits. to optimize performance, different combinations of input and output voltages and expected loads may require different inductor values. once the required value is known, the inductor core type can be chosen based on peak current and efficiency requirements. peak current in the inductor will be equal to the maximum output load current plus half of the peak-to- peak inductor ripple current. ripple current is set by the inductor value, the input and output voltage and the operating frequency. the ripple current is approximately equal to: i vv v flv ripple in out out osc o in = - ()() ()()() f osc = ltc1553l oscillator frequency = 300khz l o = inductor value table 5. recommended mosfets for ltc1553l applications typical input r ds(on) capacitance parts at 25 c (m w ) rated current (a) c iss (pf) q jc ( c/w) t jmax ( c) siliconix sud50n03-10 19 15 at 25 c 3200 1.8 175 to-252 10 at 100 c siliconix si4410dy 20 10 at 25 c 2700 150 so-8 8 at 75 c motorola mtd20n03hdl 35 20 at 25 c 880 1.67 150 d pak 16 at 100 c sgs-thomson std20n03l 23 20 at 25 c 2300 2.5 175 d pak 14 at 100 c motorola mtb75n03hdl 7.5 75 at 25 c 4025 1.0 150 dd pak 59 at 100 c irf irl3103s 14 56 at 25 c 1600 1.8 175 dd pak 40 at 100 c irf irlz44 28 50 at 25 c 3300 1.0 175 to-220 36 at 100 c fuji 2sk1388 37 35 at 25 c 1750 2.08 150 to-220
15 ltc1553l applicatio n s i n for m atio n wu u u the output capacitor in a buck converter sees much less ripple current under steady-state conditions than the input capacitor. peak-to-peak current is equal to that in the inductor, usually 10% to 40% of the total load current. output capacitor duty places a premium not on power dissipation but on esr. during an output load transient, the output capacitor must supply all of the additional load current demanded by the load until the ltc1553l can adjust the inductor current to the new value. output capacitor esr results in a step in the output voltage equal to the esr value multiplied by the change in load current. an 11a load step with a 0.05 w esr output capacitor will result in a 550mv output voltage shift; this is 19.6% of the output voltage for a 2.8v supply! because of the strong relationship between output capacitor esr and output load transient response, the output capacitor is usually chosen for esr, not for capacitance value; a capacitor with suitable esr will usually have a larger capacitance value than is needed for energy storage. electrolytic capacitors rated for use in switching power supplies with specified ripple current ratings and esr can be used effectively in ltc1553l applications. os-con electrolytic capacitors from sanyo and other manufac- turers give excellent performance and have a very high performance/size ratio for electrolytic capacitors. surface mount applications can use either electrolytic or dry tantalum capacitors. tantalum capacitors must be surge tested and specified for use in switching power supplies. low cost, generic tantalums are known to have very short lives followed by explosive deaths in switching power supply applications. avx tps series surface mount devices are popular surge tested tantalum capacitors that work well in ltc1553l applications. a common way to lower esr and raise ripple current capability is to parallel several capacitors. a typical ltc1553l application might exhibit 5a input ripple cur- rent. sanyo os-con part number 10sa220m (220 m f/ 10v) capacitors feature 2.3a allowable ripple current at 85 c; three in parallel at the input (to withstand the input ripple current) will meet the above requirements. simi- larly, avx tpse337m006r0100 (330 m f/6v) have a rated maximum esr of 0.1 w ; seven in parallel will lower the net output capacitor esr to 0.014 w . for low cost application, sanyo mv-gx series of capacitors can be used with acceptable performance. solving this equation with our typical 5v to 2.8v applica- tion with a 2 m h inductor, we get: 22 056 300 2 2 .. ()( ) ()() = khz h a m p-p peak inductor current at 11.2a load: 11 2 2 2 12 2 .. a a a += the ripple current should generally be between 10% and 40% of the output current. the inductor must be able to withstand this peak current without saturating, and the copper resistance in the winding should be kept as low as possible to minimize resistive power loss. note that in circuits not employing the current limit function, the current in the inductor may rise above this maximum under short circuit or fault conditions; the inductor should be sized accordingly to withstand this additional current. inductors with gradual saturation characteristics are often the best choice. input and output capacitors a typical ltc1553l design puts significant demands on both the input and the output capacitors. during constant load operation, a buck converter like the ltc1553l draws square waves of current from the input supply at the switching frequency. the peak current value is equal to the output load current plus 1/2 peak-to-peak ripple current, and the minimum value is zero. most of this current is supplied by the input bypass capacitor. the resulting rms current flow in the input capacitor will heat it up, causing premature capacitor failure in extreme cases. maximum rms current occurs with 50% pwm duty cycle, giving an rms current value equal to i out /2. a low esr input capacitor with an adequate ripple current rating must be used to ensure reliable operation. note that capacitor manufacturers ripple current ratings are often based on only 2000 hours (three months) lifetime at rated temperature. further derating of the input capacitor ripple current beyond the manufacturers speci- fication is recommended to extend the useful life of the circuit. lower operating temperature will have the largest effect on capacitor longevity.
16 ltc1553l feedback loop compensation the ltc1553l voltage feedback loop is compensated at the comp pin, attached to the output node of the internal g m error amplifier. the feedback loop can generally be compensated properly with an rc + c network from comp to gnd as shown in figure 8a. loop stability is affected by the values of the inductor, output capacitor, output capacitor esr, error amplifier transconductance and error amplifier compensation net- work. the inductor and the output capacitor create a double pole at the frequency: f lc = 1 2 p? (l o )(c out ) the esr of the output capacitor forms a zero at the frequency: f esr = 1 2 p (esr)(c out ) the compensation network at the error amplifier output is to provide enough phase margin at the 0db crossover frequency for the overall closed-loop transfer function. the zero and pole from the compensation network are: f z = 1 2 p (r c )(c c ) and f p = 1 2 p (r c )(c1) respectively. figure 8b shows the bode plot of the overall transfer function. the compensation value used in this design is based on the following criteria: f sw = 12f co , f z = f lc and f p = 5f co . at the closed-loop frequency f co , the attenuation due the lc filter and the input resistor divider is compensated by the gain of the pwm modulator and the gain of the error amplifier (g merr )(r c ). although a mathematical approach to frequency compensation can be used, the added complication of input and/or output filters, unknown ca- pacitor esr, and gross operating point changes with input voltage, load current variations, all suggest a more prac- tical empirical method. this can be done by injecting a transient current at the load and using an rc network box to iterate toward the final compensation values, or by obtaining the optimum loop response using a network analyzer to find the actual loop poles and zeros. applicatio n s i n for m atio n wu u u figure 8a. compensation pin hook-up 1553l f08a dac ltc1553l sense comp r c c c c1 + err 6 10 figure 8b. bode plot of the ltc1553l overall transfer function 20db/decade loop gain f p f z f co f esr frequency 1553l f08b f sw = ltc1553l switching frequency f co = closed-loop crossover frequency f lc table 6. suggested compensation network for 5v input application using multiple paralleled 330 m f avx tps output capacitors l o ( m h) c o ( m f) r c (k w )c c ( m f) c1 (pf) 1 990 1.8 0.022 680 1 1980 3.6 0.01 330 1 4950 9.1 0.01 120 2.7 990 5.1 0.01 220 2.7 1980 10 0.01 120 2.7 4950 24 0.0047 47 5.6 990 10 0.01 120 5.6 1980 20 0.0047 56 5.6 4950 51 0.0036 22
17 ltc1553l applicatio n s i n for m atio n wu u u this happens, fault will be triggered. once fault is triggered, g1 and g2 will be forced low immediately and the ltc1553l will remain in this state until v cc power supply is recycled or outen is toggled. table 6 shows the suggested compensation components for 5v input applications based on the inductor and output capacitor values. the values were calculated using mul- tiple paralleled 330 m f avx tps series surface mount tantalum capacitors as the output capacitor. the optimum component values might deviate from the suggested values slightly because of board layout and operating condition differences. an alternate output capacitor is the sanyo mv-gx series. using multiple parallel 1500 m f sanyo mv-gx capacitors for the output capacitor, table 7 shows the suggested compensation component value for a 5v input application based on the inductor and output capacitor values. table 7. suggested compensation network for 5v input application using multiple paralleled 1500 m f sanyo mv-gx output capacitors l o ( m h) c o ( m f) r c (k w )c c ( m f) c1 (pf) 1 4500 4.3 0.022 270 1 6000 5.6 0.0047 220 1 9000 8.2 0.01 150 2.7 4500 11 0.01 100 2.7 6000 15 0.01 82 2.7 9000 22 0.01 56 5.6 4500 24 0.01 56 5.6 6000 30 0.0047 39 5.6 9000 47 0.0047 27 vid0 to vid4, pwrgd and fault the digital inputs (vid0 to vid4) program the internal dac which in turn controls the output voltage. these digital input controls are intended to be static and are not designed for high speed switching. forcing v out to step from a high to a low voltage by changing the vid n pins quickly can cause fault to trip. figure 9 shows the relationship between the v out voltage, pwrgd and fault. to prevent pwrgd from interrupting the cpu unnecessarily, the ltc1553l has a built-in t pwrbad delay to prevent noise at the sense pin from toggling pwrgd. the internal time delay is designed to take about 500 m s for pwrgd to go low and 1ms for it to recover. once pwrgd goes low, the internal circuitry watches for the output voltage to exceed 115% of the rated voltage. if rated v out v out 15% 5% ?% t pwrbad t pwrgd t fault fault pwrgd 1553l f09 figure 9. pwrgd and fault layout considerations when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ltc1553l. these items are also illustrated graphically in the layout diagram of figure 10. the thicker lines show the high current paths. note that at 10a current levels or above, current density in the pc board itself is a serious concern. traces carrying high current should be as wide as possible. for example, a pcb fabricated with 2oz copper requires a minimum trace width of 0.15 " to carry 10a. 1. in general, layout should begin with the location of the power devices. be sure to orient the power circuitry so that a clean power flow path is achieved. conductor widths should be maximized and lengths minimized. after you are satisfied with the power path, the control circuitry should be laid out. it is much easier to find routes for the relatively small traces in the control circuits than it is to find circuitous routes for high current paths. 2. the gnd and sgnd pins should be shorted right at the ltc1553l. this helps to minimize internal ground disturbances in the ltc1553l and prevents differences in ground potential from disrupting internal circuit operation. this connection should then tie into the
18 ltc1553l applicatio n s i n for m atio n wu u u capacitors shown at v cc and pv cc will help provide optimum regulation performance. 5. the (+) plate of c in should be connected as close as possible to the drain of the upper mosfet. an addi- tional 1 m f ceramic capacitor between v in and power ground is recommended. 6. the sense pin is very sensitive to pickup from the switching node. care should be taken to isolate sense from possible capacitive coupling to the inductor switch- ing signal. a 0.1 m f is required between the sense pin and the sgnd pin next to the ltc1553l. 7. outen is a high impedance input and should be externally pulled up to a logic high for normal operation. 8. kelvin sense i max and i fb at q1 drain and source pins. ground plane at a single point, preferably at a fairly quiet point in the circuit such as close to the output capaci- tors. this is not always practical, however, due to physical constraints. another reasonably good point to make this connection is between the output capacitors and the source connection of the low side fet q2. do not tie this single point ground in the trace run between the low side fet source and the input capacitor ground, as this area of the ground plane will be very noisy. 3. the small signal resistors and capacitors for frequency compensation and soft start should be located very close to their respective pins and the ground ends connected to the signal ground pin through a separate trace. do not connect these parts to the ground plane! 4. the v cc and pv cc decoupling capacitors should be as close to the ltc1553l as possible. the 10 m f bypass figure 10. ltc1553l layout diagram 10 m f 10 m f 5.6k 1153l f10 0.1 m f sgnd g1 outen vid0 vid1 vid2 vid3 vid4 20 19 18 17 16 15 14 13 12 11 g2 pv cc v cc sense 0.1 m f + + v out l o pv cc r c r imax bold lines indicate high current paths c c c1 c ss c out q1 q2 + c in v in 5.6k 5.6k ltc1553l r ifb + 3 1 2 4 5 6 7 8 9 10 gnd i max i fb ss comp vid0 vid1 vid2 vid3 vid4 pwrgd fault ot 0.1 m f
19 ltc1553l applicatio n s i n for m atio n wu u u g package 20-lead plastic ssop (0.209) (ltc dwg # 05-08-1640) dimension in inches (millimeters) unless otherwise noted. package descriptio n u figure 11. single supply ltc1553l 5v to 1.8v-3.5v application with thermal monitor pwrgd fault ot vid0 to vid4 outen comp ss sgnd sense q1* q2* v cc pv cc v in 5v l o ? 2 m h 18a ltc1553l g1 i fb g2 0.1 m f 5v 1.8k 1553l f11 c c 0.01 m f r c 8.2k 5.6k 5.6k 5.6k c ss 0.1 m f 0.1 m f 0.1 m f 20 w 1n5817 10 m f gnd i max 2.7k c in ** 1200 m f 4 v out c out ?? 330 m f 7 + + c1 150pf + 5 pentium ii system dale nths-1206n02 mount thermister in close thermal proximity to q1 * siliconix sud50n03-10 ** sanyo 10mv1200gx ? coiltronics ctx02-13198 or panasonic 12ts-2r5sp ?? avx tpse337m006r0100 g20 ssop 0595 0.005 ?0.009 (0.13 ?0.22) 0 ?8 0.022 ?0.037 (0.55 ?0.95) 0.205 ?0.212** (5.20 ?5.38) 0.301 ?0.311 (7.65 ?7.90) 1234 5 6 7 8910 0.278 ?0.289* (7.07 ?7.33) 17 18 14 13 12 11 15 16 19 20 0.068 ?0.078 (1.73 ?1.99) 0.002 ?0.008 (0.05 ?0.21) 0.0256 (0.65) bsc 0.010 ?0.015 (0.25 ?0.38) dimensions do not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side dimensions do not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side * ** information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no represen- tation that the interconnection of its circuits as described herein will not infringe on existing patent rights.
20 ltc1553l 1553lf lt/tp 0198 4k ? printed in usa ? linear technology corporation 1998 linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 l (408) 432-1900 fax: (408) 434-0507 l telex: 499-3977 l www.linear-tech.com package descriptio n u dimension in inches (millimeters) unless otherwise noted. sw package 20-lead plastic small outline (wide 0.300) (ltc dwg # 05-08-1620) s20 (wide) 0396 note 1 0.496 ?0.512* (12.598 ?13.005) 20 19 18 17 16 15 14 13 1 23 4 5 6 78 0.394 ?0.419 (10.007 ?10.643) 910 11 12 0.037 ?0.045 (0.940 ?1.143) 0.004 ?0.012 (0.102 ?0.305) 0.093 ?0.104 (2.362 ?2.642) 0.050 (1.270) typ 0.014 ?0.019 (0.356 ?0.482) typ 0 ?8 typ note 1 0.009 ?0.013 (0.229 ?0.330) 0.016 ?0.050 (0.406 ?1.270) 0.291 ?0.299** (7.391 ?7.595) 45 0.010 ?0.029 (0.254 ?0.737) note: 1. pin 1 ident, notch on top and cavities on the bottom of packages are the manufacturing options. the part may be supplied with or without any of the options dimension does not include mold flash. mold flash shall not exceed 0.006" (0.152mm) per side dimension does not include interlead flash. interlead flash shall not exceed 0.010" (0.254mm) per side * ** part number description comments ltc1142 current mode dual step-down switching regulator controller dual version of ltc1148 ltc1148 current mode step-down switching regulator controller synchronous, v in 20v ltc1149 current mode step-down switching regulator controller synchronous, v in 48v, for standard threshold fets ltc1159 current mode step-down switching regulator controller synchronous, v in 40v, for logic threshold fets ltc1266 current mode step-up/down switching regulator controller synchronous n- or p-channel fets, comparator/low-battery detector ltc1430 high power step-down switching regulator controller synchronous n-channel fets, voltage mode ltc1435 high efficiency low noise synchronous step-down drive synchronous n-channel, v in 36v switching regulator ltc1438 dual high efficiency low noise synchronous step-down dual ltc1435 with power-on reset switching regulator ltc1553 5-bit programmable synchronous switching regulator high voltage version of ltc1553l controller for pentium ii processor related parts

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